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Paul D. Franzon

3D IC, Interposer (2.5D) and Multi-chip Package Design

 

3D assembly of ICs and micro-scale packaging permits substantial improvements in system performance, due to the better provisioning of interconnect bandwidth. I've been involved in several projects in this area, spanning both 3D packaging and 3D ICs. Currently, I am involved in the design and CAD for stacked 3D ICs and packages. Our main goals are to (1) demonstrate innovative methods to improve some important system metric such as power efficiency (power per unit of performance) through clever leverage of these technologies; (2) build useful sub-systems using 3D technologies and (3) build CAD flows to help design and analyze 3D designs.

Highlights of this work include the following: (1) A two chip heterogeneous processor stack that achieves a 25% improvement in performance/power through the use fast and frequent thread transfer via 3D connections; (2) A two chip ASIC partitioned at the transistor level that achieves a 21% improvemnent in performance/power through circuit partioning via 3D connections (shown above); (3) A 3-chip FFT stack that takes 25% less silicon area and 9% less power than its 2D equivalent; (4) Memory interfaces to the Tezzaron DiRAM4 3D memory, including one that uses it as a L3 cache; (4) multiple thermal tool flows for early analysis and detailed analysis of GaN on CMOS 3D integrated parts; (5) A stress analysis for for GaN on CMOS heterogeneous integration; (6) multiple CAD flows for design and verification of 3D parts.

The general thesis in our work is that 3D technologies (TSVs and/or interposers) must be employed in such a way as to bring a substantial system advantage to the application they are being used for. Potential advantages include system size, power efficiency, performance and/or cost. At the same time, the "practical" issues involved in building in 3D must be addressed. These include test and yield management, and thermal management.

Other past work in this area includes 3D packaging design, and system design exploiting interposers or "multi-chip modules".

This research was/is funded by: DARPA, Intel, SRC, Qualcomm, Sematech, NSF and Rambus.

 

Selected Publications (with links either to the submitted paper or to the version listed in IEEE Xplore):

Other Publications on this topic include the following:

  • Charles, G.; Franzon, P.D., "A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models," in Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.5, no.4, pp.541-550, April 2015 

  • Gadfort, P.; Franzon, P.D., "Millimeter-Scale True 3-D Antenna-in-Package Structures for Near-Field Power Transfer," in Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.4, no.10, pp.1574-1581, Oct. 2014 

  • Xi Chen; Ting Zhu; Davis, W.R.; Franzon, P.D., "Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits," Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.4, no.11, pp.1862,1870, Nov. 2014 

  • Franzon, Paul; Wilson, John; Li, Ming, "Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications," 3D Systems Integration Conference (3DIC), 2010 IEEE International , vol., no., pp.1,4, 16-18 Nov. 2010

  • Karim, M.A.; Franzon, P.D., "A 0.65 mW/Gbps 30 Gbps capacitive coupled 10 mm serial link in 2.5D silicon interposer," in Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on , vol., no., pp.131-134, 26-29 Oct. 2014

  • Charles, G.; Franzon, P.D., "Comparison of TSV-based PDN-design effects using various stacking topology methods," Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on , vol., no., pp.83,86, 21-24 Oct. 2012

  • Priyadarshi, S.; Harris, T. R.; Melamed, S.; Otero, C.; Kriplani, N. M.; Christoffersen, C. E.; Manohar, R.; Dooley, S.R.; Davis, W.R.; Franzon, P.D.; Steer, M.B., "Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels," Circuits, Devices & Systems, IET , vol.6, no.1, pp.35,44, January 2012

  • Priyadarshi, S.; Saunders, C.S.; Kriplani, N.M.; Demircioglu, H.; Davis, W.R.; Franzon, P.D.; Steer, M.B., "Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.31, no.10, pp.1522,1535, Oct. 2012

  • Ran Wang; Charles, G.; Franzon, P., "Modeling and compare of through-silicon-via (TSV) in high frequency," 3D Systems Integration Conference (3DIC), 2011 IEEE International , vol., no., pp.1,6, Jan. 31 2012-Feb. 2 2012

  • Harris, T.R.; Priyadarshi, S.; Melamed, S.; Ortega, C.; Manohar, R.; Dooley, S.R.; Kriplani, N.M.; Davis, W.R.; Franzon, P.D.; Steer, M.B., "A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits," Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.2, no.4, pp.660,667, April 2012

  • Melamed, S.; Thorolfsson, T.; Harris, T.R.; Priyadarshi, S.; Franzon, P.; Steer, M.B.; Davis, W.R., "Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.31, no.5, pp.676,689, May 2012

  • Priyadarshi, S.; Jianchen Hu; Won Ha Choi; Melamed, S.; Xi Chen; Davis, W.R.; Franzon, P.D., "Pathfinder 3D: A flow for system-level design space exploration," 3D Systems Integration Conference (3DIC), 2011 IEEE International , vol., no., pp.1,8, Jan. 31 2012-Feb. 2 2012

  • Franzon, P.D.; Davis, W.R.; Zheng Zhou; Priyadarshi, S.; Hogan, M.; Karnik, T.; Srinavas, G., "Coordinating 3D designs: Interface IP, standards or free form?," 3D Systems Integration Conference (3DIC), 2011 IEEE International , vol., no., pp.1,3, Jan. 31 2012-Feb. 2 2012

  • Xi Chen; Davis, W.R.; Franzon, P.D., "Adaptive clock distribution for 3D integrated circuits," Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on , vol., no., pp.91,94, 23-26 Oct. 2011

  • Thorolfsson, T.; Moezzi-Madani, N.; Franzon, P.D., "Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor," Computers & Digital Techniques, IET , vol.5, no.3, pp.198,204, May 2011

  • Charles, G.; Franzon, P.D.; Jaemin Kim; Levin, A., "Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-Droop and resonant noise in 3DIC," Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on , vol., no., pp.267,270, 23-26 Oct. 2011

  • Franzon, P.D.; Davis, W.R.; Thorolfsson, T.; Melamed, S., "3D specific systems design and CAD," Embedded Computer Systems (SAMOS), 2011 International Conference on , vol., no., pp.326,329, 18-21 July 2011

  • Franzon, Paul; Wilson, John; Li, Ming, "Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications," 3D Systems Integration Conference (3DIC), 2010 IEEE International , vol., no., pp.1,4, 16-18 Nov. 2010

  • Franzon, P.D.; Davis, W.R.; Thorolffson, T., "Creating 3D specific systems: Architecture, design and CAD," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 , vol., no., pp.1684,1688, 8-12 March 2010

  • Lipa, S.; Thorolfsson, T.; Franzon, P., "The NCSU Tezzaron design kit," 3D Systems Integration Conference (3DIC), 2010 IEEE International , vol., no., pp.1,15, 16-18 Nov. 2010

  • Melamed, S.; Thorolfsson, T.; Srinivasan, A.; Cheng, E.; Franzon, P.; Davis, W.R., "Investigation of tier-swapping to improve the thermal profile of memory-on-logic 3DICs," Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on , vol., no., pp.1,6, 6-8 Oct. 2010

  • Menglin Tsai; Klooz, A.; Leonard, A.; Appel, J.; Franzon, P., "Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC," 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on , vol., no., pp.1,8, 28-30 Sept. 2009

  • Thorolfsson, T.; Melamed, S.; Charles, G.; Franzon, P.D., "Comparative analysis of two 3D integration implementations of a SAR processor," 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on , vol., no., pp.1,4, 28-30 Sept. 2009

  • Melamed, S.; Thorolfsson, T.; Srinivasan, A.; Cheng, E.; Franzon, P.; Davis, R., "Junction-level thermal extraction and simulation of 3DICs," 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on , vol., no., pp.1,7, 28-30 Sept. 2009

  • Eun Chu Oh; Franzon, P.D., "Technology impact analysis for 3D TCAM," 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on , vol., no., pp.1,5, 28-30 Sept. 2009

  • Thorolfsson, T.; Gonsalves, K.; Franzon, P.D., "Design automation for a 3DIC FFT processor for synthetic aperture radar: A case study," Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE , vol., no., pp.51,56, 26-31 July 2009

  • Davis, W.R.; Oh, E.C.; Sule, A.M.; Franzon, P.D., "Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.17, no.4, pp.496,506, April 2009

  • Franzon, P.D.; Davis, W.R.; Steer, M.B.; Lipa, S.; Eun Chu Oh; Thorolfsson, T.; Doxsee, T.; Berkeley, S.; Shani, B.; Obermiller, K., "Design and CAD for 3D integrated circuits," Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE , vol., no., pp.668,673, 8-13 June 2008

  • Franzon, P.D.; Davis, W.R.; Steer, M.B.; Hua Hao; Lipa, S.; Luniya, S.; Mineo, C.; Julie Oh; Sule, A.; Thorolfsson, T., "Design for 3D Integration and Applications," Signals, Systems and Electronics, 2007. ISSSE '07. International Symposium on , vol., no., pp.263,266, July 30 2007-Aug. 2 2007

  • Thorolfsson, T.; Franzon, P.D., "System Design for 3D Multi-FPGA Packaging," Electrical Performance of Electronic Packaging, 2007 IEEE , vol., no., pp.171,174, 29-31 Oct. 2007

  • Eun Chu Oh; Franzon, P.D., "Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory," Custom Integrated Circuits Conference, 2007. CICC '07. IEEE , vol., no., pp.591,594, 16-19 Sept. 2007

  • Mehrotra, P.; Rao, V.; Conte, T.M.; Franzon, P.D., "Optimal chip-package codesign for high-performance DSP," Advanced Packaging, IEEE Transactions on , vol.28, no.2, pp.288,297, May 2005

  • S.F. Al-sarawi, D. Abbott, and P. Franzon, “A review of 3D Packaging Technology'', IEEE Transactions on Components, Packaging and Manufacturing Technology , Feb. 1998, Vol. 21, No. 1, pp.2-14.

  • J. Xu, J. Wilson, S. Mick, L. Luo and P. Franzon, “2.8 Gb/s Inductively Coupled Interconnect for 3-D ICs,” in Japan VLSI Symposium, June, 2005. paper, presentation

  • Jian Xu, Stephen Mick, John Wilson, Lei Luo, Karthik Chandrasakhar, Paul Franzon, “AC Coupled Interconnect for Dense 3-D Systems”, Proc. IEEE Conference on Nuclear Science and Imaging, Seattle Washington, October 2003.

  • Schaffer, T.; Glaser, A.; Franzon, P.D., "Chip-package Co-implementation of a triple DES Processor," Advanced Packaging, IEEE Transactions on , vol.27, no.1, pp.194,202, Feb. 2004

  • Xu, J.; Mick, S.; Wilson, J.; Lei Luo; Chandrasekar, K.; Erickson, E.; Franzon, P.D., "AC coupled interconnect for dense 3-D ICs," Nuclear Science, IEEE Transactions on , vol.51, no.5, pp.2156,2160, Oct. 2004

 

Contact: paulf@ncsu.edu

Last Modified: May 2016