In these projects, our goal is to determine efficient hardware algorithms, for FPGA or ASIC implementation, that permit greater bandwidth or higher throughput, or solve problems that can not be solved with pure software solutions. Our current work focuses on network security including the design and construction of Intrusion Detection Systems (IDS) and Intrusion Prevention Systems (IPS) at high data rates. While our past work in this area focused on the implementaiton of Snort and firewalls, our future work is focused on techniques to detect types of attacks that these filters can not, including anamoly detection and insider threat detection. Completed projects include the development of new hardware algorithms for the shortest prefix match problem in IP forwarding and the design of Just In Time (JIT) Optical Burst Switching hardware.

Note current work in this area is likely to proceed in the Cortical Processor project described elswhere.

Selected Publications:

• M. Aldwairi, T. Conte, P. Franzon, “Configureable String matching hardware for speeding up intrusion detection,” ACM Workshop on secure networking, Boston , Oct, 2004. Paper; Presentation

• M. Yadav, P. Hamilton, R. Sears, Y. Viniotis, T. Conte, P.D. Franzon, “A configurable classification engine for polymorphous chip architecture,” ACM BEACON Workshop, Boston , OCT. 2004. Paper, Presentation

• P. Mehrotra, P.D. Franzon, “Novel architecture for fast address lookups,” IEEE Communications Magazine, 40(11), November 2002, pp. 66-71.