Paul D. Franzon

On-Chip Interconnect


I've had a long-standing interest in the better understanding and design of on-chip interconnect. My most recent project in this area exploits the idea of using current mode circuits and on-chip equalization for the design of low-power repeaterless global on-chip interconnect. These techniques allow a reduction in on-chip power consumption of up to 51% with only a small area increase and no loss of signal integrity.

More recently, this work has been focusing on interposer interconnect, which is documented on my 3DIC page.

In the past, my group has done work on low-power repeater design, and on-chip interconnect measurement techniques.

Selected Publications

  • L. Zhang, J. Wilson, R. Bashirullah, L. Luo, JU. Xu, "Driver Pre-emphasis techniques for global on-chip buses," Proc. ISPLD, Sept. 2005. Presentation
  • S. Ma and P. Franzon: Energy Control in CMOS Buffers, IEEE Journal of Solid State Circuits , Vol. 29, No. 9, September 1994,pp. 1150--1153.
  • R. Pomerleau, G. Bilbro, and P. Franzon, “Improved delay prediction for on-chip buses,'' Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). IEEE , Piscataway , NJ , USA ; 1999; xxxii+1003 pp. p.497-501.
  • P. Franzon, “Accuracy Issues in Full-Chip Extraction'', Panel Session Chair and Organizer, DAC 1999.
  • Baribrata Biswas, Allen Glasser, Steven Lipa, Michael Steer, Paul Franzon, Dieter Griffis, Phillip Russell, “Experimental Electrical Characterization of On-Chip Interconnects'', IEEE Topical Meeting on Electrical Performance of Electronic Packaging , Oct. 1997, pp. 57-59.



Last Modified: October 2005