The data used to develop an IBIS model can be easily derived from simulations of the actual circuits or measured directly using commonly available laboratory equipment. This easily derivable data includes V-I curves for high- and low-output transitions; V-I curves for clamp diodes; high/low ramp times; component capacitance; and per-pin package resistance, inductance and capacitance. By simplifying the data collection and removing proprietary issues, the semiconductor vendors can provide IBIS models prior to, or at the same time as, the availability of first components.
Because IBIS models are behavioral, simulations run much faster than corresponding structural models. Speed improvements of 25 times are not uncommon. IBIS accomplishes this performance improvement without sacrificing accuracy by incorporating the specification of many non-linear effects of the I/O design, including package parasitics and forward-biased ESD protection diode effects.
"We have the opportunity to break open the logjam in model availability for signal integrity analysis by creating accurate, efficient models that can be delivered with the silicon," says Shiv Tasker, vice president and general manager, systems physical design group at Cadence Design Systems. "The availability of these models will have a major impact on how quickly new parts introduced by IC vendors will be designed into new products. It is therefore in the customers', and IC and EDA vendors' interest to actively encourage adoption of such critical standards as IBIS."