I have an emerging interest in the fabrication, characterization and design of nano-scale interconnect. My goals are to determine manufacturable techniques to fabricate nanowires beyond the capabilities of lithography, to characterize their properties and establish their circuit principles.

Currently, my main project in this area is entitle PEDAL : "Planar Edge Defined Alternate Layers". The goal of this project is to establish a manufacturing technology for the nano-imprinting of wire arrays with a pitch below 30 nm. The image above shows a Pd nanowire array created with this technique.

Selected Publications

• Sonkusale. S, Amsinck C. J, Nackashi D. P, Di Spigna N. H, Barlage D, Johnson M, Franzon P. D, “ Fabrication of wafer-scale, aligned Sub-25 nm naowires and templates using Planar Edge Defined Alternate Layer (PEDAL) Process,” Physica E. Low Dimensional Systems and Nanostructures. Paper