Our first two chips were fabricated via the
<a href="http://mems.mcnc.org/mumps.html">MUMPs</a> process, which
consists of the following layers:
<listing>
Layer	Size	Description		Notes
-----	-----	--------------------	-----------------------------------------
Metal	500nm	Cr-Pt			Evaporation deposited, liftoff patterned
Poly2	1.5um	2nd structural layer	Doped just as Poly1 through annealing *
Oxide2	500nm	PSG			Thin & Thick etched **
Poly1	2.0um	1st structural layer	Annealed/Phosphorus doped above & below
Oxide1	2.0um	PSG			LPCVD/RIE Dimpled 750nm deep/RIE
Poly0	500nm	0-layer polysilicon	LPCVD/masked/Reactive Ion Etched
SiN	500nm	Isolation layer		LPCVD -unetchable-
Wafer	100mm	Isolated substrate	Heavily doped n-type(100) w/ Phosphorus 
</listing>

*  creates fine-grain size and low internal stress; poly is undoped initially.
<br>
** thick etch goes through oxides until it reaches nitride or substrate.
<p>
<p>
Other known facts about the process:
<listing>
	Smallest distinguishable feature size	2um
	Young's Modulus for polysilicon layers	155.0E12 Pascals ***
	Polysilicon resistivity			1e-3 Ohm*cm
</listing>

*** assuming structures are sufficiently large that surface tensions do not
play a significant factor.