Our first two chips were fabricated via the
MUMPs process, which
consists of the following layers:
Layer Size Description Notes
----- ----- -------------------- -----------------------------------------
Metal 500nm Cr-Pt Evaporation deposited, liftoff patterned
Poly2 1.5um 2nd structural layer Doped just as Poly1 through annealing *
Oxide2 500nm PSG Thin & Thick etched **
Poly1 2.0um 1st structural layer Annealed/Phosphorus doped above & below
Oxide1 2.0um PSG LPCVD/RIE Dimpled 750nm deep/RIE
Poly0 500nm 0-layer polysilicon LPCVD/masked/Reactive Ion Etched
SiN 500nm Isolation layer LPCVD -unetchable-
Wafer 100mm Isolated substrate Heavily doped n-type(100) w/ Phosphorus
* creates fine-grain size and low internal stress; poly is undoped initially.
** thick etch goes through oxides until it reaches nitride or substrate.
Other known facts about the process:
Smallest distinguishable feature size 2um
Young's Modulus for polysilicon layers 155.0E12 Pascals ***
Polysilicon resistivity 1e-3 Ohm*cm
*** assuming structures are sufficiently large that surface tensions do not
play a significant factor.