Performance Prediction for Superscalar Processors
An ARPA-sponsored project is underway in the Electronics Research Lab to design
and build a superscalar processor. To motivate design decisions, we set out to
model the behavior and predict the performance of a variety of superscalar
microarchitectures. We ran simulations wth the ssim simulator from Stanford,
using SPECint programs as our benchmarks. We simulated a proposed design for
the ERL chip as well as several contenmporary commercial chips. The performance
metric used was CPI - Cycles Per Instruction. We also modified the ssim
simulator to more accurately model certain chips; the modified simulator, called
esim, is also described in this report.
Sanjeev Banerjia, Eric Schweitz, Mark Vilas, Saurabh Misra