Topological Description and Interconnect Delay Modeling
for Performace-Driven Partitioning and Placement of MCM Design
In this report,
we discuss some issues related to partitioning
and placement (or floorplanning) for timing-driven MCM design.
In particular, we describe how a topological description is used
to describe a combined partitioning and placement, and how linearized
circuit responses can be used to drive the tool. We give some
results that show, by using these approaches, 80% or more of
the timing and congestion constraints are met.
Christoforos Harvatis, Yusuf Tekmen, Sharad Mehrotra, Griff Bilbro, Paul Franzon