2015 3DIC AUG. 31-SEP. 2, 2015 SENDAI, JAPAN / IEEE

Technical Program

3DIC2015 Advanced Program

Advanced Program (PDF)

Aug. 31 (Mon)  
7:30 - Registration (Sendai International Center)
8:30 - 8:50 Opening Ceremony
8:50 - 9:35  Keynote (I)
  Xin Wu (Xilinx): 3D-IC Technologies and 3D FPGA
9:35 - 9:50 Break
 9:50 - 11:15 Technical Session (I) <3D Integration technologies>
  I-1.

 I-2.


 I-3.

 I-4.		 Invited talk: Subramanian Iyer (University of California at Los Angeles): Some Challenges in Scaling 3D ICs to a Broader Application Set
 Reconfigured multichip-on-wafer (CoW) hybrid Cu/oxide bonding technology for ultra-density 3D
integration using recessed oxide, thin glue adhesive and thin metal capping layers, K. W. Lee et al.
(Tohoku Univ.)
 Intermediate BEOL Process Influence on Power and Performance for 3DVLSI, H. Sarhan et al.
(CEA LETI)
 Silicon based Dry-Films Evaluation for 2.5D and 3D Wafer-level System Integration improvement, A. Jouve et al. (CEA LETI)
 11:15 - 12:20 Technical Session (II) <3D DRAM (1)>
  II-1.
 II-2.

 II-3.		 Invited talk: Robert Patti (Tezzaron Semiconductor): Progress in 3D Integrated Circuits
 Electrical Performance of High Bandwidth Memory (HBM) Interposer Channel in Terabyte/s Bandwidth Graphics Module, H. Lee et al. (KAIST)
 New Signal Skew cancellation method for 2G bps transmission in Glass and Organic Interposers to achieve 2.5D package employing Next Generation High Bandwidth Memory (HBM), S. Kariyazaki et al. (Renesas)
12:20 - 13:40 Lunch
 13:40 - 14:20 Technical Session (III) <3D DRAM (2)>
  III-1.

 III-2.		 Novel Local Stress Evaluation Method in 3D IC Using DRAM Cell Array with Planar MOS Capacitors, S. Tanikawa et al. (Tohoku Univ.)
 Characterization of Stress Distribution in Ultra-Thinned DRAM Wafer, T. Nakamura et al.
(Fujitsu laboratories / Tokyo Institute of Technology)
 14:20 - 15:00 Technical Session (IV) <Cu Metallization>
  IV-1.

 IV-2.		 Reduction of Thermal Expansion Coefficient of Electrodeposited Copper, K. Kondo et al.
(Osaka Prefecture Univ.)
 Thermal Stability of Electroplated Cupper Thin-Film Interconnections, H. Miura et al. (Tohoku Univ.)
15:00 - 15:15 Break
 15:15 - 17:45 Focus Session and Panel Discussion <3D research activities>
  FS-1.
 FS-2.

 FS-3.
 FS-4.
 FS-5.
 FS-6.
 FS-7.
 Eric Beyne (IMEC): 3D System Integration Program Research at IMEC
 Kangwook Lee (GINTI): Advanced 2.5D/3D Hetero-Integration Technologies at GINTI,
Tohoku University
 Wei-Chung Lo (ITRI): 3D Research Activities in ITRI
 Andy Heinig (Fraunhofer): Current and Future 3D Activities at Fraunhofer
 Vempati Srinivasa Rao (Institute of Microelectronics): IME's Capabilities and Programs in 2.5D/3DIC
 Pascal Vivet (CEA LETI): 3D Advanced Integration Technology for Heterogeneous Systems
 Green Daniel (DARPA): Path to 3D Heterogeneous Integration
 18:30 - 20:30 Banquet (Westin Hotel Sendai)
Sep. 1 (Tue)  
8:00 - Registration (Sendai International Center)
8:30 - 9:15 Keynote (II)
  Tadashi Kamada (DENSO): The Issues of Automated Driving Vehicle and the Expectations for Integration Technology
 9:15 - 10:40 Technical Session (V) <New TSV Materials>
  V-1.
 V-2.

 V-3.
 V-4.		 Invited talk: Rozalia Beica (Yole Development): 3D Integration: Applications and Market Trends
 Vacuum-assisted-spin-coating of Polyimide Liner for High-aspect-ratio Through-Silicon-Via (TSV)
Applications, Y. Yan et al. (Beijing Institute of Technology / Tohoku Univ.)
 Nano-Function Materials for TSV Technologies, H. Ikeda et al. (Napra / Kobe Univ.)
 High-speed via hole filling using electrophoresis of Ag nanoparticles, R. Takigawa et al.
(Kyushu Univ.)
10:40 - 10:55 Break
 10:55 - 12:20 Technical Session (VI) <3D System Related Technologies>
  VI-1.
 VI-2.

 VI-3.

 VI-4.		 Invited talk: Paul Franzon (North Carolina State University): Computing in 3D
 Comprehensive Comparison of 3D-TSV Integrated Solid-State Drives (SSDs) with Storage Class Memory and NAND Flash Memory, S. Hachiya et al. (Chuo Univ.)
 Power Saving and Noise Reduction of 28nm CMOS RF System Integration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology, C.-T. Wang et al. (TSMC)
 3D ICs: An Opportunity for Fully Integrated Power Supply, G. Pillonnet et al.
(Univ. Grenoble Alpes / CEA LETI)
12:20 - 13:40 Lunch
 13:40 - 15:05 Technical Session (VII) <Wafer Bonding/Chip Stacking>
  VII-1.
 VII-2.

 VII-3.
 VII-4.		 Invited talk: Isao Sugaya (Nikon): New Precision Wafer Bonding Technologies for 3DIC
 Permanent Wafer Bonding in the Low Temperature by Using Various Plasma Enhanced Chemical Vapour Deposition Dielectrics, S.-W. Kim et al. (IMEC)
 High Productivity Thermal Compression Bonding for 3D-IC, N. Asahi et al. (Toray Engineering)
 Transfer and Non-Transfer Stacking Technologies Based on Chip-to-Wafer Self-Assembly for High-Throughput and High-Precision Alignment and Microbump Bonding, T. Fukushima et al.
(Tohoku Univ.)
 15:05 - 16:35 Technical Session (VIII) [Poster Session]
  VIII-1.

 VIII-2.

 VIII-3.

 VIII-4.

 VIII-5.

 VIII-6.

 VIII-7.
 VIII-8.

 VIII-9.

 VIII-10.

 VIII-11.
 VIII-12.

 VIII-13.

 VIII-14.

 VIII-15.

 VIII-16.

 VIII-17.
 VIII-18.

 VIII-19.

 VIII-20.

 VIII-21.

 VIII-22.

 VIII-23.

 VIII-24.

 VIII-25.

 VIII-26.

 VIII-27.

 VIII-28.
 VIII-29.

 VIII-30.

 VIII-31.

 VIII-32.

 VIII-33.

 VIII-34.
 VIII-35.
 VIII-36. 		Copper-filled Anodized Aluminum Oxide - A potential material for chip to chip bonding -,
K. Yamashita et al. (FUJIFILM)
 Development of High-quality Low-temperature (120°C) PECVD-SiN Films by Organosilane,
H. Taka et al. (TAIYO NIPPON SANSO)
 Vertical integration after Stacking (ViaS) Process for Low-cost and Low-stress 3D Silicon Integration, K. Sueoka et al. (IBM Research Tokyo)
 All-wet TSV filling with highly adhesive displacement plated Cu seed layer, K. Ohta et al.
(Kansai Univ.)
 Variation of Thermal Stress in TSV Structures Caused by Crystallinity of Electroplated Copper Interconnections, K. Suzuki et al. (Tohoku Univ.)
 Twice-Etched Silicon Approach for Via-Last Through-Silicon-Via with a Parylene-HT Liner,
T. T. Bui et al. (AIST)
 Air-Gap/SiO2 Liner TSVs with Improved Electrical Performance, Z. Wang et al. (Tsinghua Univ.)
 An Ultra-Fast Temporary Bonding and Release Process Based on Thin Photolysis Polymer in 3D Integration, T. Y. Tsai et al. (National Chiao Tung Univ.)
 Copper Micro and Nano Particles Mixture for 3D Interconnections Application, Y. Y. Dai et al.
(Nanyang Technological Univ. )
 Mitigating Thermo Mechanical Stress in High-Density 3D-LSI by Dielectric Liners in Cu-Through Silicon Via - μ-RS and μ-XRD Analysis, M. Mariappan et al. (Tohoku Univ.)
 TSV Etching and VDP Process Integration for High Reliability, T. Murayama et al. (ULVAC)
 Electrical Investigation of Cu Pumping in Through-Silicon Vias for BEOL Reliability in 3D Integration,
C.-A. Cheng et al. (National Chiao Tung Univ.)
 Long Term Efficacy of Ultrathin Ti Passivation Layer for Achieving Low Temperature, Low Pressure Cu-Cu Wafer-on-Wafer Bonding, A. K. Panigrahi et al. (Indian Institute of Technology)
 Fast filling of Through-silicon Via (TSV) with Conductive Polymer/Metal Composites,
J. Kawakita et al. (NIMS)
 Room-Temperature Bonding Mechanism of Compliant Bump with Ultrasonic Assist, K. Iwanabe et al.
(Kyushu Univ.)
 Influential Factors in Low-Temperature Direct Bonding of Silicon Dioxide, R. Shirahama et al.
(Kyushu Institute of Tech.)
 Warpage Analysis of Organic Substrates for 2.1D Packaging, S. Kohara et al. (IBM Research-Tokyo)
 Guard-Ring Monitoring System for Inspecting Defects in TSV-Based Data Buses, Y. Araga et al.
(AIST)
 Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume, M. Hashizume et al. (Tokushima Univ.)
 Improved Access Pattern for ROB Soft Error Rate Mitigation Based on 3D Integration Technology, C. Song et al. (National Univ. Defense Technology)
 Boundary Condition Independent Multi Junctions Compact Thermal Models for 2.5D Multi-die Packages, A. Raghupathy et al. (Electronic Cooling Solutions)
 Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit, M. Hashizume et al. (Tokushima Univ.)
 Congestion-Aware Optimal Techniques for Assigning Inter-Tier Signals to 3D-Vias in a 3DIC,
G. Neela et al. (Univ. Southern California)
 On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs, H. Yotsuyanagi et al. (Tokushima Univ.)
 Crosstalk-Included Eye-Diagram Estimation for High-speed Silicon, Organic, and Glass Interposer Channels on 2.5D/3D IC, S. Choi et al. (KAIST)
 Consideration of Microbump Layout for Reduction of Local Bending Stress Due to CTE Mismatch in 3D IC, H. Kino et al. (Tohoku Univ.)
 Characterization of the Mechanical Stress Impact on Device Electrical Performance in the CMOS and III-V HEMT/HBT Heterogeneous Integration Environment, P. D. Franzon et al. (NCSU)
 Design of a 3-D Stacked Floating-point Goldschmidt Divider, J. Tada et al. (Yamagata Univ.)
 Modeling and Analysis of Defects in Through Silicon Via Channel For Non-invasive Fault Isolation,
D. H. Jung et al. (KAIST)
 Investigation of Effects of Metalization on Heat Spreading in Bump-Bonded 3D Systems,
S. Melamed et al. (AIST)
 Enabling Automatic System Design Optimization through Assembly Design Kits, A. Heinig et al.
(Fraunhofer)
 Cost Modeling and Analysis for the Design, Manufacturing and Test of 3D-ICs, A. Gruenewald et al.
(Univ. Siegen)
 Proposed Static Timing Analysis Framework for Extracted 3D Integrated Circuits (3D-STA), D. S. Khalil et al. (Ain Shams Univ.)
 Noise Coupling Modeling and Analysis of Through Glass Via(TGV), I. Hwang et al. (KAIST)
TSV Noise Coupling in 3D IC Using Guard Ring, R. R. Reddy et al. (Indian Institute of Technology)
 Power Tile Optimization and Packaging for Efficient Temperature Management of ASIC’s
in Networking Applications, S. Narasimhan et al. (Juniper Networks)
 16:35 - 17:40 Technical Session (IX) <3D Imager and Device>
  IX-1.

 IX-2.

 IX-3. 		Invited talk: Tomoharu Ogita (Sony): Technology and Overview of Sony's 3D Stacked CMOS Image Sensor
 Three-Dimensional Integrated Circuits and Stacked CMOS Image Sensors using Direct Bonding of SOI Layers, M. Goto et al. (NHK)
 Fine-Grained 3-D Integrated Circuit Fabric using Vertical Nanowires, M. Rahman et al.
(Univ. Massachusetts Amherst)
18:00 - 19:30 Rump Session (Wine&Cheese)
  Moderator: Paul Franzon (NCSU)
 Panelist : Sung Kyu Lim (Georgia Tech)
 Panelist : Kazuyuki Higashi (Toshiba)
 Panelist : Toshifumi Irisawa (AIST)
 Panelist : Subramanian Iyer (UCLA)
 Panelist : Paul Enquist (Ziptronix)
 Panelist : Yasumitsu Orii (IBM)
Sep. 2 (Wed)  
8:00 - Registration (Sendai International Center)
8:30 - 9:15  Keynote (III)
  Chung H. Lam (IBM Research): Neuromorphic Semiconductor Memory
 9:15 - 10:40 Technical Session (X) <3D Thermal Issues>
  X-1.

 X-2.
 X-3.

 X-4. 		Invited talk: Gamal Refai-Ahmed (Xilinx): A Holistic View of Chip-Level Thermal Architecture
from Heterogeneous Stacked Dice to System Level in Telecoms Applications
 Thermal Simulation of Heterogeneous GaN/InP/Silicon 3DIC Stacks, P. Franzon et al. (NCSU)
 Temperature-Aware Online Testing of Power-Delivery TSVs, S.-Y. Huang et al.
(National Tsing Hua Univ.)
 Graphite-based Heat Spreaders for Hotspot Mitigation in 3D ICs, C. Santos et al. (CEA LETI)
10:40 - 10:55 Break
 10:55 - 12:20 Technical Session (XI) <Interposer Technologies>
  XI-1.
 XI-2.
 XI-3.

 XI-4. 		Invited talk: Joungho Kim (KAIST): Active Si Interposer for 3D IC Integrations
 Processing Active Devices on Si Interposer and Impact on Cost, D. Velenis et al. (IMEC)
 Novel Silicon Interposer Platform With Low-Loss Through-Silicon Vias, H. Oh et al.
(Georgia Institute of Technology)
 Investigating Temperature-Dependent Die Curvature During Silicon Interposer Integration,
B. Vianne et al. (STMicroelectronics)
12:20 - 12:30 Closing Remark
  (Lunch)
13:30 - 17:30 Social Program <GINTI Tour>
Presentation time
Keynote: 45min (40min+5min)
Invited paper: 25min (20min+5min)
Regular paper: 20min (17min+3min)
Focus Session (FS): 15min